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Research Insight: Kinsus Tech identifies three challenges for larger AI chip packages
Brief published October 30, 2026 ยท Original source published October 28, 2026
Original reporting by Yunnie Cheng at digitimes.com.
Automated brief. Verify important details at the original source.
What happened
At the 2026 TPCA Show, Kinsus Interconnect Technology R&D vice president Ting-Hao Lin presented findings on the packaging challenges created by AI computing demand. Lin identified three challenges tied to the industry shift toward larger chip package form factors. The evidence centers on substrate materials needing to meet new requirements to support this trend, though the article excerpt does not fully detail all three challenges or the specific material properties involved.
Why it matters
Substrate and packaging constraints are increasingly a bottleneck for AI chip scaling. When a major interconnect substrate supplier flags specific engineering barriers at an industry forum, it signals that hardware supply chains may face friction points beyond chip design itself, which is directly relevant to anyone planning AI infrastructure or sourcing advanced packaging capacity.
What to watch
Whether Kinsus or other substrate suppliers publish fuller technical specifications for the material requirements Lin referenced, and how packaging partners respond to the identified constraints as larger form factor demand grows.